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80c32/80c52 1 rev. i september 18, 1998 1. description temic's 80c52 and 80c32 are high performance cmos versions of the 8052/8032 nmos single chip 8 bit microcontroller. the fully static design of the temic 80c52/80c32 allows to reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the 80c52 retains all the features of the 8052: 8 k bytes of rom; 256 bytes of ram; 32 i/o lines; three 16 bit timers; a 6-source, 2-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuits. in addition, the 80c52 has 2 software-selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the ram, the timers, the serial port and the interrupt system continue to function. in the power down mode the ram is saved and all other functions are inoperative. the 80c32 is identical to the 80c52 except that it has no on-chip rom. temic's 80c52/80c32 are manufactured using scmos process which allows them to run from 0 up to 44 mhz with vcc = 5 v. temic's 80c52 and 80c32 are also available at 16 mhz with 2.7 v < vcc < 5.5 v. 80c32: romless version of the 80c52 80c32/80c52-l16: low power version vcc: 2.7 5.5 v freq: 0-16 mhz 80c32/80c52-12: 0 to 12 mhz 80c32/80c52-16: 0 to 16 mhz 80c32/80c52-20: 0 to 20 mhz 80c32/80c52-25: 0 to 25 mhz 80c32/80c52-30: 0 to 30 mhz 80c32/80c52-36: 0 to 36 mhz 80c32-40: 0 to 40 mhz (1) 80c32-42: 0 to 42 mhz (1) 80c32-44: 0 to 44 mhz (1) notes: 1. 0 to 70 c temperature range. 2. for other speed and temperature range availability, please contact your sales office. 2. features power control modes 256 bytes of ram 8 kbytes of rom (80c52) 32 programmable i/o lines three 16 bit timer/counters 64 k program memory space 64 k data memory space fully static design 0.8 m cmos process boolean processor 6 interrupt sources programmable serial port temperature range: commercial, industrial, automotive, military 3. optional secret rom: encryption secret tag: identification number cmos 0 to 44 mhz single chip 8bit microcontroller
80c32/80c52 2 rev. i september 18, 1998 4. interface serial i/o port cpu p0 8bit internal bus parallel i/o ports & external bus t0 int0 t1 int1 xtal1 xtal2 ea ale psen wr rd ad0ad7 a8a15 rst vcc vss timer 0 timer 1 timer 2 interrupt unit oscillator & timing ram 256 bytes rom 8 kbytes rxd txd p3 p2 p1 t2 t2ex figure 1. block diagram
80c32/80c52 3 rev. i september 18, 1998 80c32/80c52 80c32/80c52 diagrams are for reference only. package sizes are not to scale. dil lcc qfp p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 nc vcc p0.0/a0 p0.1/a1 p0.2/a2 p0.3/a3 p0.4/a4 p1.5 p1.6 p1.7 rst rxd/p3.0 nc txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 p0.5/a5 p0.6/a6 p0.7/a7 ea nc ale psen p2.7/a15 p2.6/a14 p2.5/a13 wr/p3.6 rd/p3.7 xtal2 xtal1 vss nc p2.0/a8 p1.5 p1.6 p1.7 rxd/p3.0 txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 wr/p3.6 rd/p3.7 xtal2 xtal1 vss nc p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 rst nc p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 nc vcc a0/p0.0 p0.4/a4 p0.5/a5 p0.6/a6 p0.7/a7 ea nc ale psen p2.7/a15 p2.6/a14 p2.5/a13 a1/p0.1 a2/p0.2 a3/p0.3 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 14 15 16 17 13 18 19 23 22 21 20 26 25 24 27 28 5 4 3 2 1 6 44 43 42 41 40 figure 2. pin configuration
80c32/80c52 4 rev. i september 18, 1998 5. pin description 5.1. vss circuit ground potential. 5.2. vcc supply voltage during normal, idle, and power down operation. 5.3. port 0 port 0 is an 8 bit open drain bi-directional i/o port. port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pullups when emitting 1's. port 0 also outputs the code bytes during program verification in the 80c52. external pullups are required during program verification. port 0 can sink eight ls ttl inputs. 5.4. port 1 port 1 is an 8 bit bi-directional i/o port with internal pullups. port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (iil, on the data sheet) because of the internal pullups. port 1 also receives the low-order address byte during program verification. in the 80c52, port 1 can sink/ source three ls ttl inputs. it can drive cmos inputs without external pullups. 2 inputs of port 1 are also used for timer/counter 2 : p1.0 [t2]: external clock input for timer/counter 2. p1.1 [t2ex]: a trigger input for timer/counter 2, to be reloaded or captured causing the timer/counter 2 interrupt. 5.5. port 2 port 2 is an 8 bit bi-directional i/o port with internal pullups. port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (ill, on the data sheet) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses (movx @dptr). in this application, it uses strong internal pullups when emitting 1's. during accesses to external data memory that use 8 bit addresses (movx @ri), port 2 emits the contents of the p2 special function register. it also receives the high-order address bits and control signals during program verification in the 80c52. port 2 can sink/source three ls ttl inputs. it can drive cmos inputs without external pullups. 5.6. port 3 port 3 is an 8 bit bi-directional i/o port with internal pullups. port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (ill, on the data sheet) because of the pullups. it also serves the functions of various special features of the temic 51 family, as listed below.
80c32/80c52 5 rev. i september 18, 1998 port pin alternate function p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 rxd (serial input port) txd (serial output port) int0 (external interrupt 0) int1 (external interrupt 1) td (timer 0 external input) t1 (timer 1 external input) wr (external data memory write strobe) rd (external data memory read strobe) port 3 can sink/source three ls ttl inputs. it can drive cmos inputs without external pullups. 5.7. rst a high level on this for two machine cycles while the oscillator is running resets the device. an internal pull-down resistor permits power-on reset using only a capacitor connected to vcc. as soon as the reset is applied (vin), port 1, 2 and 3 are tied to one. this operation is achieved asynchronously even if the oscillator does not start-up. 5.8. ale address latch enable output for latching the low byte of the address during accesses to external memory. ale is activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data memory access at which time one ale pulse is skipped. ale can sink/source 8 ls ttl inputs. it can drive cmos inputs without an external pullup. 5.9. psen program store enable output is the read strobe to external program memory. psen is activated twice each machine cycle during fetches from external program memory. (however, when executing out of external program memory, two activations of psen are skipped during each access to external data memory). psen is not activated during fetches from internal program memory. psen can sink/source 8 ls ttl inputs. it can drive cmos inputs without an external pullup. 5.10. ea when ea is held high, the cpu executes out of internal program memory (unless the program counter exceeds 1 fffh). when ea is held low, the cpu executes only out of external program memory. ea must not be floated. 5.11. xtal1 input to the inverting amplifier that forms the oscillator. receives the external oscillator signal when an external oscillator is used. output of the inverting amplifier that forms the oscillator. this pin should be floated when an external oscillator is used.
80c32/80c52 6 rev. i september 18, 1998 6. idle and power down operation figure 3. shows the internal idle and power down clock configuration. as illustrated, power down operation stops the oscillator. idle mode operation allows the interrupt, serial port, and timer blocks to continue to function, while the clock to the cpu is gated off. these special modes are activated by software via the special function register, pcon. its hardware address is 87h. pcon is not bit addressable. figure 3. idle and power down hardware pcon: power control register (msb) (lsb) 76543210 smod gf1 gf0 pd idl symbol position name and function smod pcon.7 double baud rate bit when set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3. pcon.6 reserved the value read from this bit is indeterminate. do not set this bit. pcon.5 reserved the value read from this bit is indeterminate. do not set this bit. pcon.4 reserved the value read from this bit is indeterminate. do not set this bit. gf1 pcon.3 generalpurpose flag bit gf0 pcon.2 generalpurpose flag bit pd (1) pcon.1 power down bit. setting this bit activates power down operation cleared by hardware when an interrupt or reset occurs. set to activate the powerdown mode. if idl and pd are both set, pd takes precedence. idl (1) pcon.0 idle mode bit cleared by hardware when an interrupt or reset occurs. set to activate the idle mode. if idl and pd are both set, pd takes precedence. 1. if 1's are written to pd and idl at the same time. pd takes, precedence. the reset value of pcon is (000x0000).
80c32/80c52 7 rev. i september 18, 1998 6.1. idle mode the instruction that sets pcon.0 is the last instruction executed before the idle mode is activated. once in the idle mode the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle. table 1. describes the status of the external pins during idle mode. there are three ways to terminate the idle mode. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating idle mode. the interrupt is serviced, and following reti, the next instruction to be executed will be the one following the instruction that wrote 1 to pcon.0. the flag bits gf0 and gf1 may be used to determine whether the interrupt was received during normal execution or during the idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when idle mode is terminated by an enabled interrupt, the service routine can examine the status of the flag bits. the second way of terminating the idle mode is with a hardware reset. since the oscillator is still running, the hardware reset needs to be active for only 2 machine cycles (24 oscillator periods) to complete the reset operation. 6.2. power down mode the instruction that sets pcon.1 is the last executed prior to entering power down. once in power down, the oscillator is stopped. the contents of the onchip ram and the special function register is saved during power down mode. the hardware reset initiates the special fucntion register. in the power down mode, vcc may be lowered to minimize circuit power consumption. care must be taken to ensure the voltage is not reduced until the power down mode is entered, and that the voltage is restored before the hardware reset is applied which freezes the oscillator. reset should not be released until the oscillator has restarted and stabilized. table 1. describes the status of the external pins while in the power down mode. it should be noted that if the power down mode is activated while in external program memory, the port data that is held in the special function register p2 is restored to port 2. if the data is a 1, the port pin is held high during the power down mode by the strong pullup, t1, shown in figure 4. table 1. status of the external pins during idle and power down modes mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 port data port data port data port data idle external 1 1 floating port data address port data power down internal 0 0 port data port data port data port data power down external 0 0 floating port data port data port data 6.3. stop clock mode due to static design, the temic 80c32/c52 clock speed can be reduced until 0 mhz without any data loss in memory or registers. this mode allows step by step utilization, and permits to reduce system power consumption by bringing the clock frequency down to any value. at 0 mhz, the power consumption is the same as in the power down mode.
80c32/80c52 8 rev. i september 18, 1998 6.4. i/o ports the i/o buffers for ports 1, 2 and 3 are implemented as shown in figure 4. figure 4. i/o buffers in the 80c52 (ports 1, 2, 3) when the port latch contains a 0, all pfets in figure 4 are off while the nfet is turned on. when the port latch makes a 0-to-1 transition, the nfet turns off. the strong pfet, t1, turns on for two oscillator periods, pulling the output high very rapidly. as the output line is drawn high, pfet t3 turns on through the inverter to supply the ioh source current. this inverter and t form a latch which holds the 1 and is supported by t2. when port 2 is used as an address port, for access to external program of data memory, any address bit that contains a 1 will have his strong pullup turned on for the entire duration of the external memory access. when an i/o pin on ports 1, 2, or 3 is used as an input, the user should be aware that the external circuit must sink current during the logical 1-to-0 transition. the maximum sink current is specified as itl under the d.c. specifications. when the input goes below approximately 2 v, t3 turns off to save icc current. note, when returning to a logical 1, t2 is the only internal pullup that is on. this will result in a slow rise time if the user's circuit does not force the input line high. 6.5. oscillator characteristics xtal1 and xtal2 are the input and output respectively, of an inverting amplifier which is configured for use as an on-chip oscillator, as shown in figure 5. either a quartz crystal or ceramic resonator may be used. figure 5. crystal oscillator to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected as shown in figure 6. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed.
80c32/80c52 9 rev. i september 18, 1998 figure 6. external drive configuration 7. hardware description same as for the 80c51, plus a third timer/counter. 7.1. timer/event counter 2 timer 2 is a 16 bit timer/counter like timers 0 and 1, it can operate either as a timer or as an event counter. this is selected by bit c/t2 in the special function register t2con (figure 1.). it has three operating modes : acaptureo, aautoloado and abaud rate generatoro, which are selected by bits in t2con as shown in table 2. in the capture mode there are two options which are selected by bit exen2 in t2con; if exen2 = 0, then timer 2 is a 16 bit timer or counter which upon overflowing sets bit tf2, the timer 2 overflow bit, which can be used to generate an interrupt. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively, (rcap2l and rcap2h are new special function register in the 80c52). in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt. table 2. timer 2 operating modes rclk + tclk cp/rl2 tr2 mode 0 0 1 x 0 1 x x 1 1 1 0 16 bit auto-reload 16 bit capture baud rate generator (off) the capture mode is illustrated in figure 7.
80c32/80c52 10 rev. i september 18, 1998 t2 0 1 tr2 t2con.2 c/t2 t2con.1 osc 12 t2ex exf2 t2con.6 rcap2l rcap2h tl2 (8 bits) th2 (8 bits) tf2 t2con.7 exen2 t2con.3 timer 2 interrupt request overflow figure 7. timer 2 in capture mode in the auto-reload mode there are again two options, which are selected by bit exen2 in t2con.if exen2 = 0, then when timer 2 rolls over it does not only set tf2 but also causes the timer 2 register to be reloaded with the 16 bit value in registers rcap2l and rcap2h, which are preset by software. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex will also trigger the 16 bit reload and set exf2. the auto-reload mode is illustrated in figure 8. t2 0 1 tr2 t2con.2 c/t2 t2con.1 osc 12 t2ex exf2 t2con.6 rcap2l rcap2h tl2 (8 bits) th2 (8 bits) tf2 t2con.7 exen2 t2con.3 timer 2 interrupt request overflow figure 8. timer in autoreload mode
80c32/80c52 11 rev. i september 18, 1998 t2con (s:c8h) timer/counter 2 control register 76543210 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7 tf2 timer 2 overflow flag tf2 is not set if rclk= 1 or tclk= 1. set by hardware when timer 2 overflows. must be cleared by software 6 exf2 timer 2 external flag exf2 does not cause an interrupt in up/down counter mode (dcen= 1). set by hardware if exen2= 1 when a negative transition on t2ex pin is detected. 5 rclk receive clock bit clear to select timer 1 as the timer receive baud rate generator for the serial port in modes 1 and 3. set to select timer 2 as the timer receive baud rate generator for the serial port in modes 1 and 3. 4 tclk transmit clock bit clear to select timer 1 as the timer transmit baud rate generator for the serial port in modes 1 and 3. set to select timer 2 as the timer transmit baud rate generator for the serial port in modes 1 and 3. 3 exen2 timer 2 external enable bit clear to ignore events on t2ex pin for timer 2. set to cause a capture or reload when a negative transition on t2ex pin is detected unless timer 2 is being used as the baud rate generator for the serial port. 2 tr2 timer 2 run control bit clear to turn off timer 2. set to to turn on timer 2. 1 c/t2# timer 2 counter/timer select bit clear for timer operation: timer 2 counts the divideddown system clock. set for counter operation: timer 2 counts negative transitions on external pin t2. 0 cp/rl2# capture/reload bit cp/rl2 # is ignored and timer 2 is forced to autoreload on timer 2 overflow if rclk= 1 or tclk= 1. clear to autoreload on timer 2 overflows or negative transitions on t2ex pin if exen2= 1. set to capture on negative transitions on t2ex pin if exen2= 1 reset value= 0000 0000b
80c32/80c52 12 rev. i september 18, 1998 7.2. 80c52 with secret rom temic offers 80c52 with the encrypted secret rom option to secure the rom code contained in the 80c52 microcontrollers. the clear reading of the program contained in the rom is made impossible due to an encryption through several random keys implemented during the manufacturing process. the keys used to do such encryption are selected randomwise and are definitely different from one microcontroller to another. this encryption is activated during the following phases : everytime a byte is addressed during a verify of the rom content, a byte of the encryption array is selected. movc instructions executed from external program memory are disabled when fetching code bytes from internal memory. ea is sampled and latched on reset, thus all state modification are disabled. for further information please refer to the application note (anm053) available upon request. 7.3. 80c52 with secret tag temic offers special 64-bit identifier called asecret tago on the microcontroller chip. the secret tag option is available on both romless and masked microcontrollers. the secret tag feature allows serialization of each microcontroller for identification of a specific equipment. a unique number per device is implemented in the chip during manufacturing process. the serial number is a 64-bit binary value which is contained and addressable in the special function registers (sfr) area. this secret tag option can be read-out by a software routine and thus enables the user to do an individual identity check per device. this routine is implemented inside the microcontroller rom memory in case of masked version which can be kept secret (and then the value of the secret tag also) by using a rom encryption. for further information, please refer to the application note (anm031) available upon request. 8. electrical characteristics 8.1. absolute maximum ratings (1) in commercial and industrial temp range ambiant temperature under bias: c = commercial 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . i = industrial 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . a = automotive 40 c to +125 c . . . . . . . . . . . . . . . . . . . . . m = military 55 c to +125 c . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65 c to + 150 c . . . . . . . . . . . . . . . . . voltage on vcc to vss 0.5 v to + 7 v . . . . . . . . . . . . . . . voltage on any pin to vss 0.5 v to vcc + 0.5 v . . . . . . . . . . . . . . . power dissipation 1 w (2) . . . . . . . . . . . . . . . . . . . notes: 1. stresses at or above those listed under a absolute maximum ratingso may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. 2. this value is based on the maximum allowable die temperature and the thermal resistance of the package .
80c32/80c52 13 rev. i september 18, 1998 8.2. dc parameters commercial and industrial table 3. dc parameters ta= 0 c to 70 c; vss= 0 v; vcc= 5 v 10 %; f= 0 to 44 mhz ta= 40 c + 85 c; vss= 0 v; vcc= 5 v 10 %; f= 0 to 36 mhz symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 vcc + 0.5 v vih1 input high voltage (for xtal and rst) 0.7 vcc vcc + 0.5 v vol output low voltage (port 1, 2 and 3) 0.3 0.45 1.0 v v v iol= 100 m a iol= 1.6 ma (4) iol= 3.5 ma vol1 output low voltage (port 0, ale, psen ) 0.3 0.45 1.0 v v v iol= 200 m a iol= 3.2 ma (4) iol= 7.0 ma voh output high voltage port 1, 2, 3 vcc 0.3 v ioh= 10 m a vcc 0.7 v ioh= 30 m a vcc 1.5 v ioh= 60 m a vcc= 5 v 10 % voh1 output high voltage (port 0, ale, psen ) vcc 0.3 v ioh= 200 m a vcc 0.7 v ioh= 3.2 ma vcc 1.5 v ioh= 7.0 ma vcc= 5 v 10 % iil logical 0 input current (ports 1, 2 and 3) 50 m a vin= 0.45 v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2 and 3) 650 m a vin= 2.0 v ipd power down current 50 m a vcc= 2.0 v to 5.5 v (3) rrst rst pulldown resistor 50 200 kohm cio capacitance of i/o buffer 10 pf 1 mhz, ta= 25 c icc power supply current freq= 1 mhz icc op icc idle freq= 6 mhz icc op icc idle freq 12 mhz icc op= 1.25 freq (mhz) + 5 ma icc idle= 0.36 freq (mhz) + 2.7 ma 1.8 1 10 4 ma ma ma ma vcc= 5.5 v (1) (2) notes: 1. icc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl= 5 ns, vil= vss + .5 v, vih= vcc .5 v; xta l2 n.c. ; ea= rst= port 0= vcc. icc would be slighty higher if a crystal oscillator used. 2. idle icc is measured with all output pins disconnected ; xtal1 driven with tclch, tchcl= 5 ns, vil= vss + 5 v, vih= vcc .5 v ; xtal2 n.c; port 0= vcc; ea= rst= vss. 3. power down icc is measured with all output pins disconnected; ea= port 0= vcc; xtal2 n.c. ; rst= vss. 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the vols of ale and ports 1 and 3. t he noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions du ring bus operations. in the worst cases (capacitive loading 100 pf), the noise pulse on the ale line may exceed 0.45 v may exceed 0,45 v with maxi vol peak 0.6 v. a schmitt trigger use is not necessary.
80c32/80c52 14 rev. i september 18, 1998 8.3. dc parameters automotive table 4. dc parameters ta= 40 c + 125 c; vss= 0 v; vcc= 5 v 10 %; f= 0 to 36 mhz symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 vcc + 0.5 v vih1 input high voltage (for xtal and rst) 0.7 vcc vcc + 0.5 v vol output low voltage (port 1, 2 and 3) 0.3 0.45 1.0 v v v iol= 100 m a iol= 1.6 ma (4) iol= 3.5 ma vol1 output low voltage (port 0, ale, psen ) 0.3 0.45 1.0 v v v iol= 200 m a iol= 3.2 ma (4) iol= 7.0 ma voh output high voltage port 1, 2 and 3 vcc 0.3 v ioh= 10 m a vcc 0.7 v ioh= 30 m a vcc 1.5 v ioh= 60 m a vcc= 5 v 10 % voh1 output high voltage (port 0, ale, psen ) vcc 0.3 v ioh= 200 ma vcc 0.7 v ioh= 3.2 ma vcc 1.5 v ioh= 7.0 ma vcc= 5 v 10 % iil logical 0 input current (ports 1, 2 and 3) 75 m a vin= 0.45 v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2 and 3) 750 m a vin= 2.0 v ipd power down current 75 m a vcc= 2.0 v to 5.5 v (3) rrst rst pulldown resistor 50 200 kohm cio capacitance of i/o buffer 10 pf 1 mhz, ta= 25 c icc power supply current freq= 1 mhz icc op icc idle freq= 6 mhz icc op icc idle freq 12 mhz icc op= 1.25 freq (mhz) + 5 ma icc idle= 0.36 freq (mhz) + 2.7 ma 1.8 1 10 4 ma ma ma ma vcc= 5.5 v (1) (3) notes: 1. icc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl= 5 ns, vil= vss + .5 v, vih= vcc .5 v; xta l2 n.c. ; ea= rst= port 0= vcc. icc would be slighty higher if a crystal oscillator used. 2. idle icc is measured with all output pins disconnected ; xtal1 driven with tclch, tchcl= 5 ns, vil= vss + 5 v, vih= vcc .5 v ; xtal2 n.c; port 0= vcc; ea= rst= vss. 3. power down icc is measured with all output pins disconnected; ea= port 0= vcc; xtal2 n.c. ; rst= vss. 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the vols of ale and ports 1 and 3. t he noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions du ring bus operations. in the worst cases (capacitive loading 100 pf), the noise pulse on the ale line may exceed 0.45 v may exceed 0,45 v with maxi vol peak 0.6 v. a schmitt trigger use is not necessary.
80c32/80c52 15 rev. i september 18, 1998 8.4. dc parameters military table 5. dc parameters ta= 55 c + 125 c; vss= 0 v; vcc= 5 v 10 %; f= 0 to 36 mhz symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 vcc + 0.5 v vih1 input high voltage (for xtal and rst) 0.7 vcc vcc + 0.5 v vol output low voltage (port 1, 2 and 3) 0.45 v iol= 1.6 ma (4) vol1 output low voltage (port 0, ale, psen) 0.45 v iol= 3.2 ma (4) voh output high voltage (port 1, 2 and 3) 2.4 v ioh= 60 m a vcc= 5 v 10 % 0.75 vcc v ioh= 25 m a 0.9 vcc v ioh= 10 m a voh1 output high voltage (port 0 in external bus mode, ale, pen) 2.4 v ioh= 400 m a vcc= 5 v 10 % 0.75 vcc v ioh= 150 m a 0.9 vcc v ioh= 40 m a iil logical 0 input current (ports 1, 2 and 3) 75 m a vin= 0.45 v ili input leakage current +/ 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2 and 3) 750 m a vin= 2.0 v ipd power down current 75 m a vcc= 2.0 v to 5.5 v (3) rrst rst pulldown resistor 50 200 k w cio capacitance of i/o buffer 10 pf mhz, ta= 25 c icc power supply current freq= 1 mhz icc op icc idle freq= 6 mhz icc op icc idle freq 12 mhz icc op= 1.25 freq (mhz) + 5 ma icc idle= 0.36 freq (mhz) + 2.7 ma 1.8 1 10 4 ma ma ma ma vcc= 5.5 v notes: 1. icc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl= 5 ns, vil= vss + .5 v, vih= vcc .5 v; xta l2 n.c. ; ea= rst= port 0= vcc. icc would be slighty higher if a crystal oscillator used. 2. idle icc is measured with all output pins disconnected ; xtal1 driven with tclch, tchcl= 5 ns, vil= vss + 5 v, vih= vcc .5 v ; xtal2 n.c; port 0= vcc; ea= rst= vss. 3. power down icc is measured with all output pins disconnected; ea= port 0= vcc; xtal2 n.c. ; rst= vss. 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the vols of ale and ports 1 and 3. t he noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions du ring bus operations. in the worst cases (capacitive loading 100 pf), the noise pulse on the ale line may exceed 0.45 v may exceed 0,45 v with maxi vol peak 0.6 v. a schmitt trigger use is not necessary.
80c32/80c52 16 rev. i september 18, 1998 8.5. dc parameters low voltage commercial and industrial table 6. dc characteristics ta= 0 c to 70 c; vcc= 2.7 v to 5.5 v; vss= 0 v; f= 0 to 16 mhz ta= 40 c to 85 c; vcc= 2.7 v to 5.5 v symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 vcc + 0.5 v vih2 input high voltage to rst for reset 0.7 vcc vcc + 0.5 v vih1 input high voltage to xtal1 0.7 vcc vcc + 0.5 v vpd power down voltage to vcc in pd mode 2.0 5.5 v vol output low voltage (ports 1, 2, 3) 0.45 v iol= 0.8 ma (4) vol1 output low voltage port 0, ale, psen 0.45 v iol= 1.6 ma (4) voh output high voltage ports 1, 2, 3 0.9 vcc v ioh= 10 m a voh1 output high voltage (port 0 in external bus mode), ale, psen 0.9 vcc v ioh= 40 m a iil logical 0 input current ports 1, 2, 3 50 m a vin= 0.45 v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2, 3) 650 m a vin= 2.0 v ipd power down current 50 m a vcc= 2.0 v to 5.5 v (3) rrst rst pulldown resistor 50 200 k w cio capacitance of i/o buffer 10 pf mhz, t a = 25 c notes: 1. icc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl= 5 ns, vil= vss + .5 v, vih= vcc .5 v; xta l2 n.c. ; ea = rst = port 0 = vcc. icc would be slighty higher if a crystal oscillator used. 2. idle icc is measured with all output pins disconnected ; xtal1 driven with tclch, tchcl= 5 ns, vil= vss + 5 v, vih= vcc .5 v ; xtal2 n.c; port 0= vcc; ea= rst= vss. 3. power down icc is measured with all output pins disconnected; ea= port 0= vcc; xtal2 n.c. ; rst= vss. 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the vols of ale and ports 1 and 3. t he noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions du ring bus operations. in the worst cases (capacitive loading 100 pf), the noise pulse on the ale line may exceed 0.45 v may exceed 0,45 v with maxi vol peak 0.6 v. a schmitt trigger use is not necessary.
80c32/80c52 17 rev. i september 18, 1998 table 7. maximum icc (ma) operating (1) idle (2) frequency/vcc 2.7 v 3 v 3.3 v 5.5 v 2.7 v 3 v 3.3 v 5.5 v 1 mhz 0.8 ma 1 ma 1.1 ma 1.8 ma 400 m a 500 m a 600 m a 1 ma 6 mhz 4 ma 5 ma 6 ma 10 ma 1.5 ma 1.7 ma 2 ma 4 ma 12 mhz 8 ma 10 ma 12 ma 2.5 ma 3 ma 3.5 ma 16 mhz 10 ma 12 ma 14 ma 3 ma 3.8 ma 4.5 ma freq > 12 mhz (vcc= 5.5 v) icc (ma)= 1.25 freq (mhz) + 5 icc idle (ma)= 0.36 freq (mhz) + 2.7 notes: 1. icc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl= 5 ns, vil= vss + .5 v, vih= vcc .5 v; xta l2 n.c. ; ea= rst= port 0= vcc. icc would be slighty higher if a crystal oscillator used. 2. idle icc is measured with all output pins disconnected ; xtal1 driven with tclch, tchcl= 5 ns, vil= vss + 5 v, vih= vcc .5 v ; xtal2 n.c; port 0= vcc; ea= rst= vss. 3. power down icc is measured with all output pins disconnected; ea= port 0= vcc; xtal2 n.c. ; rst= vss. 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the vols of ale and ports 1 and 3. t he noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions du ring bus operations. in the worst cases (capacitive loading 100 pf), the noise pulse on the ale line may exceed 0.45 v may exceed 0,45 v with maxi vol peak 0.6 v. a schmitt trigger use is not necessary. figure 9. icc test condition, idle mode. all other pins are disconnected figure 10. icc test condition, active mode. all other pins are disconnected
80c32/80c52 18 rev. i september 18, 1998 figure 11. icc test condition, power down mode. all other pins are disconnected note: tclch= tchcl= 5ns figure 12. clock signal waveform for icc tests in active and idle modes 8.6. explanation of the ac symbol each timing symbol has 5 characters. the first character is always a ato (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. example : tavll= time for address valid to ale low. tllpl= time for ale low to psen low. a: address. c: clock. d: input data. h: logic level high i: instruction (program memory contents). l: logic level low, or ale. p: psen. q: output data. r: read signal. t: time. v: valid. w: write signal. x: no longer a valid logic level. z: float.
80c32/80c52 19 rev. i september 18, 1998 8.7. ac parameters ta= 0 to + 70 c; vss= 0 v; vcc= 5 v 10 %; f= 0 to 44 mhz ta= 0 to +70 c; vss= 0 v; 2.7 v < vcc < 5.5 v; f= 0 to 16 mhz ta= 40 to + 85 c; vss= 0 v; 2.7 v < vcc < 5.5 v; f= 0 to 16 mhz ta= 55 + 125 c; vss= 0 v; vcc= 5 v 10 %; f= 0 to 36 mhz (load capacitance for port 0, ale and psen= 100 pf; load capacitance for all other outputs= 80 pf) table 8. external program memory characteristics (values in ns) 16 mhz 20 mhz 25 mhz 30 mhz 36 mhz 40 mhz 42 mhz 44 mhz symbol parameter min max min max min max min max min max min max min max min max tlhll ale pulse width 110 90 70 60 50 40 35 30 tavll address valid to ale 40 30 20 15 10 9 8 7 tllax address hold after ale 35 35 35 35 35 30 25 17 tlliv ale to valid instr in 185 170 130 100 80 70 65 65 tllpl ale to psen 45 40 30 25 20 15 13 12 tplph psen pulse width 165 130 100 80 75 65 60 54 tpliv psen to valid instr in 125 110 85 65 50 45 40 35 tpxix input instr hold after psen 0 0 0 0 0 0 0 0 tpxiz input instr float after psen 50 45 35 30 25 20 15 10 tpxav psen to address valid 55 50 40 35 30 25 20 15 taviv address to valid instr in 230 210 170 130 90 80 75 70 tplaz psen low to address float 10 10 8 6 5 5 5 5 tpliv tplaz ale psen port 0 port 2 a0a7 a0a7 instr in instr in instr in address or sfrp2 address a8a15 address a8a15 12 tclcl taviv tlhll tavll tlliv tllpl tplph tpxav tpxix tpxiz tllax figure 13. external program memory read cycle
80c32/80c52 20 rev. i september 18, 1998 table 9. external data memory characteristics (values in ns) 16 mhz 20 mhz 25 mhz 30 mhz 36 mhz 40 mhz 42 mhz 44 mhz symbol parameter min max min max min max min max min max min max min max min max trlrh rd pulse width 340 270 210 180 120 100 90 80 twlwh wr pulse width 340 270 210 180 120 100 90 80 tllax address hold after ale 85 85 70 55 35 30 25 25 trldv rd to valid data in 240 210 175 135 110 90 80 70 trhdx data hold after rd 0 0 0 0 0 0 0 0 trhdz data float after rd 90 90 80 70 50 45 40 35 tlldv ale to valid data in 435 370 290 235 170 150 140 130 tavdv address to valid data in 480 400 320 260 190 180 175 170 tllwl ale to wr or rd 150 250 135 170 120 130 90 115 70 100 60 95 55 90 50 85 tavwl address to wr or rd 180 180 140 115 75 65 60 55 tqvwx data valid to wr transition 35 35 30 20 15 10 8 6 tqvwh data setup to wr transition 380 325 250 215 170 160 150 140 twhqx data hold after wr 40 35 30 20 15 10 8 6 trlaz rd low to address float 0 0 0 0 0 0 0 0 twhlh rd or wr high to ale high 35 90 35 60 25 45 20 40 20 40 15 35 13 33 13 33 tqvwh tllax ale psen wr port 0 port 2 a0a7 data out address or sfrp2 tavwl tllwl tqvwx address a8a15 or sfr p2 twhqx twhlh twlwh figure 14. external data memory write cycle
80c32/80c52 21 rev. i september 18, 1998 ale psen rd port 0 port 2 a0a7 data in address or sfrp2 tavwl tllwl trlaz address a8a15 or sfr p2 trhdz twhlh trlrh tlldv trhdx tavdv tllax figure 15. external data memory read cycle table 10. serial port timing shift register mode (values in ns) 16 mhz 20 mhz 25 mhz 30 mhz 36 mhz 40 mhz 42 mhz 44 mhz symbol parameter min max min max min max min max min max min max min max min max txlxl serial port clock cycle time 750 600 480 400 330 250 230 227 tqvxh output data setup to clock rising edge 563 480 380 300 220 170 150 140 txhqx output data hold after clock rising edge 63 90 65 50 45 35 30 25 txhdx input data hold after clock rising edge 0 0 0 0 0 0 0 0 txhdv clock rising edge to input data valid 563 450 350 300 250 200 180 160 figure 16. shift register timing waveforms
80c32/80c52 22 rev. i september 18, 1998 table 11. external clock drive characteristics (xtal1) symbol parameter min max unit fclcl oscillator frequency 44 mhz tclcl oscillator period 22.7 ns tchcx high time 5 ns tclcx low time 5 ns tclch rise time 5 ns tchcl fall time 5 ns figure 17. external clock drive waveforms figure 18. ac testing input/output waveforms ac inputs during testing are driven at vcc 0.5 for a logic a1o and 0.45 v for a logic a0o. timing measurements are made at vih min for a logic a1o and vil max for a logic a0o. figure 19. float waveforms for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded voh/vol level occurs. iol/ioh 20 ma.
80c32/80c52 23 rev. i september 18, 1998 figure 20. clock waveforms this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propagation also varies from output to output and component. typically though (t a = 25 c fully loaded) rd and wr propagation delays are approximately 50 ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications.
80c32/80c52 24 rev. i september 18, 1998 9. ordering information package type p: pdil 40 s: plcc 44 f1: pqfp 44 (foot print 13.9 mm) f2: pqfp 44 (foot print 12.3 mm) v: vqfp (1.4 mm) t: tqfp (1.0 mm) d: cdil 40 q: cqfp 44 r: lcc 44 c: side brazed 40 (.6) j: j leaded lcc temperature range blank : commercial i : industrial a : automotive m : military part number 80c52 rom 8 k 8 80c32 external rom 80c52c secret rom version 80c52t secret tag version 80c32e radiation tolerant 80c52e radiation tolerant customer rom code i xxx s 80c52c 12 : 12 mhz version 16 : 16 mhz version 20 : 20 mhz version 25 : 25 mhz version 30 : 30 mhz version 36 : 36 mhz version 40 : 40 mhz version (1) 42 : 42 mhz version (1) 44 : 44 mhz version (1) l16 : low power (vcc: 2.7-5.5 v freq: 0-16 mhz) 36 d blank = mhs standards /883 = mil std 883 class b or s sb/sc = scc 9000 level b/c shxxx = special customer request fhxxx = flight models (space) ehxxx = engineering models (space) mhxxx = mechanical parts (space) lhxxx = life test parts (space) : r = tape and reel : rd = tape and reel dry pack : d = dry pack 1. only for 80c32 at commercial range.
80c32/80c52 25 rev. i september 18, 1998 temp. range packages speed (mhz) std process 80c32/52 rt process 80c32e l16 16,00 20,00 25,00 30,00 36,00 mil flows mil flows space flows m d r j q x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x s c j r x x x x x x x x x x x x x x x x x x x x x

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